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This work presents the design of a dedicated parallel architecture for connected component analysis. Categorized in one-dimensional array processors, for an image of nxn pixels, the proposed architecture has n-1 linear PE's, n2 CAM memory modules, and a tree structure of (&)-I switches allowing communication through the global bus in O(1og n) unit of(More)
T h s work presents a CAM-based design for a linear array of processors. Called LAPCAM, the simcance of this architecture is, in particular, that it provides the Mul-ti-Mode Access (MMA) memories such as FIFO, RAM. normal CAM. and interactive CAM modes. In this paper. we present the organization of the LAPCAM and we demonstrate the ability to solve global(More)
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