— In this work an approach to converting a number in two's complement representation to a minimum signed-digit representation is proposed. The novelty in this work is that this conversion is done from left-to-right and right-to-left concurrently. Hence, the execution time is significantly decreased, while the area overhead is small.
This paper gives an introduction to the silicon-on-insula-tor (SOI) CMOS technology and presents the major advantages and disadvantages of using SOI. It also presents the design of a comparator, which has been sent for manufacturing, designed in a 0.13 µm partially depleted SOI CMOS process. The comparator is a first step towards the design of a complete… (More)
A 10-bit low power track-and-hold (T&H) circuit aimed for the front-end of a pipelined analog-to-digital (A/D) converter has been designed. The T&H is sampling at 80MS/s, has a 30MHz analog bandwidth and was designed in a 0.18µm CMOS process with a supply voltage of 1.8 Volt. A switched capacitor topology applying correlated double sampling is used for the… (More)