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A flash analog-to-digital converter is proposed that employs a new dynamic element matching architecture. The architecture uses a new strategy of incorporating switches in the voltage reference generator that allows lower hardware complexity and higher conversion speed than comparable converters. The converter has been mod-eled and simulated on a behavioral(More)
This paper gives an introduction to the silicon-on-insulator (SOI) CMOS technology and presents the major advantages and disadvantages of using SOI. It also presents the design of a comparator, which has been sent for manufacturing, designed in a 0.13 /spl mu/m partially depleted SOI CMOS process. The comparator is a first step towards the design of a(More)
A 10-bit low power track-and-hold (T&H) circuit aimed for the front-end of a pipelined analog-to-digital (A/D) converter has been designed. The T&H is sampling at 80MS/s, has a 30MHz analog bandwidth and was designed in a 0.18µm CMOS process with a supply voltage of 1.8 Volt. A switched capacitor topology applying correlated double sampling is used for the(More)
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