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We report extremely low specific contact resistivity ͑␳ c ͒ nonalloyed Ohmic contacts to n-type In 0.53 Ga 0.47 As, lattice matched to InP. Contacts were formed by oxidizing the semiconductor surface through exposure to ultraviolet-generated ozone, subsequently immersing the wafer in ammonium hydroxide ͑NH 4 OH, 14.8 normality͒, and finally depositing(More)
We examine the feasibility of developing bipolar transistors with current-gain and power-gain cutoff frequencies of 1-3 THz. High bandwidths are obtained by scaling; the critical limits to such scaling are the requirements that the current density increase in proportion to the square of bandwidth and that the metal-semiconductor contact resistivities vary(More)
A complete reliability study of the high-frequency characteristics for nMOSFETs on InGaAs channel with Al<sub>2</sub>O<sub>3</sub>/HfO<sub>2</sub> gate dielectric is presented. DC gate voltage stress causes an increase in the transconductance frequency dispersion. Stress induced border traps degrade the maximum DC-transconductance, but do not react at high(More)
We report InP/InGaAs/InP double heterojunction bipolar transistors (DHBT) fabricated using a conventional mesa structure. The devices employ a 14 nm highly doped InGaAs base and a 60 nm InP collector containing an InGaAs/InAlAs superlattice grade. Devices employing a 400 nm emitter exhibit a maximum f<sub>T</sub> = 660 GHz with a 218 GHz f <sub>max</sub> -(More)
  • E. Lind
  • 2015
We present compact modeling, DC and RF characterization of lateral and vertical nanowire MOSFETs. Lateral tri-gate nanowire devices on InP substrates have demonstrated a maximum g<sub>m</sub>=2.95 mS/&#x03BC;m at V<sub>DS</sub>=0.5 V, and f<sub>T</sub>/f<sub>max</sub>=290/350 GHz. Vertical gate-all-around InAs wires integrated on Si substrates have(More)
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