Erik L. Hedberg

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An 18Mb DRAM has been designed in a 3.34, 0.5-pm CMOS process. The array consists of four independent, self-contained 4.5Mb quadrants. The chip output configuration defaults to 1 Mb x 18 for optimization of wafer screen tests, while 3 .34 or 5.04 operation is selected by choosing one of two M2 configurations. Selection of 2Mb x 9 or 1 Mb x 18 operation with(More)
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