Erich Marschner

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In March 1980, the US Department of Defense (DoD) launched the Very High Speed Integrated Circuits program to advance the state of the art in highspeed integrated circuit technology, specifically for defense systems. In 1981 the Institute for Defense Analyses (IDA) arranged a workshop to define the requirements for such a standard. The DoD used the final(More)
1 Cadence Design Systems, Inc. 2 Structured Design Verification, Inc. ABSTRACT Rapid design of complex chips requires acquisition and integration of reusable IP blocks. Effective reuse of an IP block requires documenting the designer's understanding of the block, particularly its interface requirements and any assumptions about its internal operation.(More)
VHDL is a critical language for RTL design and is a major component of the $200+ million RTL simulation market1. Many users prefer to use VHDL for RTL design as the language continues to provide desired characteristics in design safety, flexibility and maintainability2. While VHDL has provided significant value for digital designers since 1987, it has had(More)
Note that local variables and first match are not in the domain of the mapping. Throughout, “unclocked SVA sequence” means “unclocked SVA sequence without local variables or first match”. Similarly, “clocked SVA sequence” means “clocked SVA sequence without local variables or first match”. In the following abstract grammars, b denotes a boolean expression,(More)
The VHSIC hardware description language (VHDL) is now an IEEE standard (VHDL 1076). The original language (VHDL 7.2) has been refined by the IEEE, and the resulting language has broader capabilities than originally anticipated. The features and capabilities of VHDL and the refinements made by the IEEE over the original language are discussed. Examples of(More)
Integrated circuit design logic can be conceptually split into multiple types of partitions for interdomain analysis. For example, a modern design typically has a power domain partition, a clock domain partition, and a reset domain partition. Historically, inter-domain analysis is confined to logic verification across boundaries of the same domain types(More)
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