Erich Marschner

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VHDL is a critical language for RTL design and is a major component of the $200+ million RTL simulation market1. Many users prefer to use VHDL for RTL design as the language continues to provide desired characteristics in design safety, flexibility and maintainability2. While VHDL has provided significant value for digital designers since 1987, it has had(More)
Assumptions: • The SVA semantics is understood to be from SVA 3.1, revised to include neutral semantics and to fix errata. The SVA neutral semantics is understood to be generalized to empty words, with the only change being that w, b |= sva initial assert property Q iff if |w| > 0 and ¯ w 0 = b, then w |= sva Q [Comments? Is this what people expect?] • PSL(More)
Integrated circuit design logic can be conceptually split into multiple types of partitions for inter-domain analysis. For example, a modern design typically has a power domain partition, a clock domain partition, and a reset domain partition. Historically, inter-domain analysis is confined to logic verification across boundaries of the same domain types(More)
New England is bracing for a snowstorm that could bring as much as two feet of snow in the next day or two. By the time you read this, we'll know a) whether the forecasters were correct and b) how well we hardy New Englanders were able to cope. I often joke that I'm going to encourage my children to be meteorologists because that's the one job where,(More)
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