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A programmable radio baseband signal processor is one of the essential enablers of software- defined radio. As wireless standards evolve, the processing power needed for baseband processing increases dramatically and the underlying hardware needs to cope with various standards or even simultaneously maintaining several radio links. Meanwhile, the maximum(More)
3G evolution towards HSPA (High Speed Packet Access) and LTE (Long-Term Evolution) is ongoing which will substantially increase the throughput with higher spectral efficiency. This paper presents the system architecture of an LTE modem based on a programmable baseband processor. The architecture includes a baseband processor that handles processing such as(More)
Rapid evolution of wireless standards and the increasing demand for multi-standard products make traditional fixed-function hardware for baseband processing too rigid. Programmable solutions are needed. At the same time, traditional DSP architectures cannot meet cost and power requirements in handheld devices. As a response to this, a new processor(More)
With the rapid evolution of wireless standards and increasing demand for multi-standard products, the need for flexible RF and baseband solutions is growing. Flexibility is required to be able to adapt to unstable standards and requirements without costly hardware re-spins, and also to enable hardware reuse between products and between multiple wireless(More)
A real SDR/JTRS (Software Defined Radio / Joint Tactical Radio System) transceiver can be linked to any public or private radio system. The transceiver baseband processor must adapt to the actual radio channel coding and shall manage ISI, mobility, synchronization, and different interferers. Current baseband solutions are unable to fulfil these requirements(More)
Fully programmable radio baseband processor architecture is presented. The architecture is based on a DSP processor core and number flexible accelerators, connected via a configurable network. Design choices are motivated by the inherent properties of the baseband algorithms used in different types of radio systems. A large degree of hardware reuse between(More)
A programmable baseband processor architecture is presented. The architecture is based on a specialized DSP processor core and a number accelerators connected via a configurable network. The focus of this paper is the DSP core itself. A novel type of instructions operating on vectors of complex data is used. Implementation of a demonstrator chip and(More)
Efficient programmable baseband processors are important in order to enable true multi-standard radio platforms and software defined radio systems. In programmable processors, the memory sub-system accounts for a large part of both the area and power consumption. This paper presents a methodology for designing memory efficient multi-standard baseband(More)