Eric MacDonald

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In this paper, a technique for weighted pseudo-random built-in self-test (BIST) of VLSI circuits is proposed, which uses special scan cells and a new weight selection algorithm to achieve low power dissipation. It is based on weighted pseudo-random scan testing in which only 3 weight values are used - 2 fixed values (0 or 1) and 1 random value (0.5). A new(More)
—Partially depleted silicon-on-insulator (PD-SOI) technology has garnered more attention recently with regards to replacing traditional bulk-silicon technology as the mainstream technology of choice for high-performance/low-power digital applications. The increase in performance is due to the buried oxide layer, which provides a dramatic decrease in the(More)
Layer-by-layer deposition of materials to manufacture parts-better known as three-dimensional (3D) printing or additive manufacturing-has been flourishing as a fabrication process in the past several years and now can create complex geometries for use as models, assembly fixtures, and production molds. Increasing interest has focused on the use of this(More)