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In this paper, a technique for weighted pseudo-random built-in self-test (BIST) of VLSI circuits is proposed, which uses special scan cells and a new weight selection algorithm to achieve low power dissipation. It is based on weighted pseudo-random scan testing in which only 3 weight values are used - 2 fixed values (0 or 1) and 1 random value (0.5). A new(More)
Low power consumption and radiation hardness are generally competing requirements for space electronics as well as many Earth-bound high reliability applications. Fault tolerance typically requires redundancy and reconfigurability to ensure correct functional operation in the presence of errors. However, this runs contrary to the requirement for reduced(More)
The proliferation of both Partially Depleted Silicon-On-Insulator (PD-SOI) technology and domino circuit styles has allowed for increases in circuit performance beyond that of scaling traditional bulk CMOS static circuits. However, interactions between dynamic circuit styles and PD-SOI complicate testing. This paper describes the issues of testing domino(More)
We propose a tuning method for MEMS gyroscopes based on evolutionary computation to efficiently increase the sensitivity of MEMS gyroscopes through tuning. The tuning method was tested for the second generation JPL/Boeing Post-resonator MEMS gyroscope using the measurement of the frequency response of the MEMS device in open-loop operation We also report on(More)
—Partially depleted silicon-on-insulator (PD-SOI) technology has garnered more attention recently with regards to replacing traditional bulk-silicon technology as the mainstream technology of choice for high-performance/low-power digital applications. The increase in performance is due to the buried oxide layer, which provides a dramatic decrease in the(More)