Learn More
A new method for generating weighted random patterns for testing LSSD logic chips and modules is described. Advantages in using weighted random versus either deterministic or random test patterns are discussed. An algorithm for calculating an initial set of input-weighting factors and a procedure for obtaining complete stuck-fault coverage are presented. An(More)
Embedded linear feedback shift registers can be used for logic component self-test. The issue of test coverage is addressed by circuit modification, where necessary, of random-pattern-resistant fault nodes. Also given is a procedure that supports net-level diagnosis for structured logic in the presence of random test-pattern generation and signature(More)
This paper describes a heuristic method for generating test patternsfor Programmable Logic Arrays (PLAs). Exploiting the regular structure of PLAs, both random and deterministic test-pattern generation techniques are combined to achieve coverage o f crosspoint defects. Patterns to select or deselect product terms are generated through direct inspection of(More)
  • B Rohleisch, A Kolbl, +90 authors Multi
  • 2008
Reducing power dissipation after technology mapping by structural transformations. Circuit activity based logic synthesis for low power reliable operations. " IEEE Advanced Automatic test pattern generation and redundancy identification techniques. circuit design using synthesis and optimization. On average power dissipation and random pattern testability(More)
  • 1