Epifanio Gaona-Ramírez

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In the search for new paradigms to simplify multi-threaded programming, Transactional Memory (TM) is currently being advocated as a promising alternative to deadlock-prone lock-based synchronization. In this way, future many-core CMP architectures may need to provide hardware support for TM. On the other hand, power dis-sipation constitutes a first class(More)
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