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The Princeton University Behavioral Synthesis System (PUBSS) is a high-level synthesis system targeted to control-dominated machines. PUBSS accepts a VHDL subset, in which the design can be described as multiple communicating processes plus registers, and generates a register-transfer implementation. This paper describes the compiler wi(h emphasis on the(More)
This paper reviews the interconnect and package design of a heterogeneous stacked-silicon FPGA. Up to five dice from two die types are mounted on a passive silicon interposer. A hardware- and software-scalable FPGA family can be created by mixing different combinations of these two die types. The FPGA, inside a low-temperature co-fired ceramic (LTCC)(More)
A polynomial accelerator implemented with a custom high-dynamic-range number representation operates up to 534MHz in the slowest speed grade on a 28nm FPGA, a clock rate that a typical FPGA tool flow cannot achieve. This design tutorial shows how to achieve a physically scalable and high-speed numerical design by partitioning it into a cascade of identical(More)
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