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* This paper deals with the problem of automated test pattern generation for large digital circuits. A distributed approach based on Genetic Algorithms is presented, which exploits the computational power of workstation networks to solve the problem even for the largest circuits. A prototypical system named GATTO is presented: the experimental results show(More)
* The use of parallel architectures for the solution of CPU and memory critical problems in the Electronic CAD area has been limited up to now by several factors , like the lack of efficient algorithms, the reduced portability of the code, and the cost of the hardware. However, portable message-passing libraries are now available, and the same code runs on(More)
Due to the continuous increase in the size and complexity of VLSI circuits, Automated Test Pattern Generation (ATPG) [ABFr90] is now a major problem from the industrial and economic point of view. As far as the single stuck-at fault model is considered, efficient algorithms have been devised for combinational and small sequential networks. Very large(More)
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