Enrique Prefasi

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This work presents experimental results of a 6 order band-pass continuous-time sigma-delta modulator that uses transmission lines as resonators. It has been implemented in 0.35u SiGe BiCMOS technology. The modulator tolerates two clock cycles of excess loop delay and has similar clock jitter sensitivity than that of an equivalent switched capacitor(More)
This paper shows the operating principle and experimental results of a new continuous-time sigma–delta modulator architecture. The proposed modulator does not require a multibit quantizer nor a mismatch-shaping digital-to-analog converter to produce a multibit noise-shaped output. Instead, its quantizer encodes the loop filter output in a binary signal(More)
This work presents a prototype low pass continuous time sigma delta modulator which uses transmission lines in its loop filter rather than capacitive integrators. As has been shown in prior theoretical work, such a structure allows to desensitize the modulator against clock jitter and excess loop delay. The prototype single-bit modulator was designed for an(More)
The receiver architecture proposed in this brief seizes the subsampling properties of continuous-time sigma–delta ( ) modulators based on distributed resonators to construct a quadrature receiver. The proposed architecture is based on a low-pass modulator that subsamples an intermediate frequency signal around the sampling frequency and does not require(More)