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R. Iris Bahar Erica A. Frohm Charles M. Gaona Gary D. Hachtel Enrico Macii y Abelardo Pardo Fabio Somenzi University of Colorado Department of Electrical and Computer Engineering Boulder, CO 80309 Abstract In this paper we present theory and experiments on the Algebraic Decision Diagrams (ADD's). These diagrams extend BDD's by allowing values from an(More)
Regarding nite state machines as Markov chains facilitates the application of probabilistic methods to very large logic synthesis and formal veriication problems. In this paper we present symbolic algorithms to compute the steady-state probabilities for very large nite state machines (up to 10 27 states). These algorithms, based on Algebraic Decision(More)
2 ADD-Based Timing Analysis The problem of calculatin& the timing r8poose of a combin... tionallogic block can be formulated as follows: GiYen a combinational block, find the set of input vectors for which the length of the critical path, under a .pecified mode of operation and a gate delay model, is maximum; the length of the critical path gi~ the overall(More)
We propose a new algorithm for automatic clock-gating insertion applicable at the register transfer level (RTL). The basic rationale of our approach is to eliminate redundant computations performed by temporally unobservable blocks through aggressive exploitation of observability don't care (ODC) conditions. ODCs are efficiently detected from an RTL(More)
In this paper we present algorithms for approximate FSM traversal based on state space decomposition. The original FSM is partitioned in sub-machines, and each of them is traversed separately; the result is an over-estimation of the set of reachable states. Several traversal strategies are discussed. Good partitioning is important for the performance of the(More)
Power and reliability are known to be intrinsically conflicting metrics: traditional solutions to improve reliability such as redundancy, increase of voltage levels, and up-sizing of critical devices do contrast with traditional low-power solutions, which rely on small devices and scaled supply voltages. The emergence of Negative Bias Temperature(More)
As power consumption of the clock tree in modern VLSI designs tends to dominate, measures must be taken to keep it under control. This paper introduces an approach for reducing clock power based on clock gating. We present a methodology that, starting from an RTL description, automatically generates a set of constraints for driving the construction of the(More)
For portable applications, long battery lifetime is the ultimate design goal. Therefore, the availability of battery and voltage converter models providing accurate estimates of battery lifetime is key for system-level low-power design frameworks. In this paper, we introduce a discrete-time model for the complete power supply subsystem that closely(More)
A bstract—The growing market of mobile, battery-powered electronic systems (e.g., cellular phones, personal digital assistants, etc.) demands the design of microelectronic circuits with low power dissipation. More generally, as density, size, and complexity of the chips continue to increase , the difficulty in providing adequate cooling might either add(More)