Enric Herrero

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Next generation tiled microarchitectures are going to be limited by off-chip misses and by on-chip network usage. Furthermore, these platforms will run an heterogeneous mix of applications with very different memory needs, leading to significant optimization opportunities. Existing adaptive memory hierarchies use either centralized structures that limit the(More)
This paper presents the Distributed Cooperative Caching, a scalable and energy-efficient scheme to manage chip multiprocessor (CMP) cache resources. The proposed configuration is based in the Cooperative Caching framework [3] but it is intended for large scale CMPs. Both centralized and distributed configurations have the advantage of combining the benefits(More)
The widespread adoption of chip multiprocessors in recent years has increased the number of applications simultaneously accessing DRAM memories. Therefore, memory access patterns have also changed and this has reduced row buffer locality significantly, degrading performance and energy efficiency. Furthermore, concurrent execution of applications also has(More)
Current trends in CMPs indicate that the core count will increase in the near future. One of the main performance limiters of these forthcoming microarchitectures is the latency and high demand of the on-chip network and the off-chip memory communication. One of the main trade-offs when searching an optimal cache hierarchy is the sharing degree of cache(More)
The TRAMS (Terascale Reliable Adaptive MEMORY Systems) project addresses in an evolutionary way the ultimate CMOS scaling technologies and paves the way for revolutionary, most promising beyond-CMOS technologies. In this abstract we show the significant variability levels of future 18 and 13nm device bulk-CMOS technologies as well as its dramatic effect on(More)
Soft error rates are estimated based on worst-case architectural vulnerability factor (AVF). Therefore, it makes tracking real-time accurate AVF very attractive to computer designers: more accurate AVF numbers will allow turning on more features at runtime while keeping the promised SDC and DUE rates. This paper presents a hardware mechanism based on linear(More)
Current trends in CMPs indicate that the core count will increase in the near future. One of the main performance limiters of these forthcoming microarchitectures is the latency and high-demand of the on-chip network and the off-chip memory communication. To optimize the usage of on-chip memory space and reduce off-chip traffic several techniques have(More)
We have recently reported the development and validation of quantum mechanical (QM)-based hydrophobic descriptors derived from the parametrized IEF/PCM-MST continuum solvation model for 3D-QSAR studies within the framework of the Hydrophobic Pharmacophore (HyPhar) method. In this study we explore the applicability of these descriptors to the analysis of(More)
Since the development of structure-activity relationships about 50 years ago, 3D-QSAR methods belong to the most refined ligand-based in silico techniques for prediction of biological data using physicochemical molecular fields. In this scenario, this study reports the development and validation of quantum mechanical (QM)-based hydrophobic descriptors(More)
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