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The Tree-based FPGA offers better density and timing determinism than traditional mesh-based FPGA. Moreover, thanks to its multilevel structure, it offers greater easiness to balance dual signals in terms of routing resources number. In this paper, we study the use of the Wave Dynamic Differential Logic (WDDL) on a custom tree-based FPGA of 2048 cells. The(More)
A novel 3D Tree-based Multilevel FPGA architecture that unifies two unidirectional programmable interconnection network is presented in this paper. In a Tree based architecture, the interconnects are arranged in a multi-level network with the logic blocks placed at different Tree levels using Butterfly-Fat-Tree network topology. 2D physical layout(More)
This paper presents an improved Tree-based architecture that unifies two unidirectional programmable networks: A predictible downward network based on the Butter y-Fat-Tree topology, and an upward network using hierarchy. Studies based on Rent's Rule show that switch requirements in this architecture grow slower than in traditional Mesh topologies. New(More)
An innovative 3D physical design exploration methodology for Tree-based FPGA architecture is presented in this paper. In a Tree-based FPGA architecture, the interconnects are arranged in a multidimensional network with the logic unites and switch blocks placed at different levels, using a Butterfly-Fat Tree network topology. A 3D physical design exploration(More)
This paper presents an improved cluster-based Mesh architecture. This architecture has a depopulated intra-cluster interconnect, and presents a new hierarchical topology for the switch box which unifies a downward and an upward unidirectional networks. Experimental results of 20 MCNC benchmarks show that density is improved and interconnect area requirement(More)
In this paper, we propose placement and routing techniques to deal with the timing unbalance problem in Wave Dynamic Differential Logic (WDDL) circuits. First, we study the impact of placement on the delay unbalance in a Tree-based FPGA. Then, we propose an adaptation to the Pathfinder routing algorithm to improve the delay balance. The experimental results(More)
The technological evolution involves a higher number of physical defects in circuits after manufacturing. One of the future challenge is to find a way to use a maximum of defected manufactured circuits. In this paper, multiple techniques are proposed to avoid defects in the cluster local interconnect of a SRAM-based Mesh of Clusters FPGA. Using defect(More)