Emna Amouri

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This paper presents an improved cluster-based Mesh architecture. This architecture has a depopulated intra-cluster interconnect, and presents a new hierarchical topology for the switch box which unifies a downward and an upward unidirectional networks. Experimental results of 20 MCNC benchmarks show that density is improved and interconnect area requirement(More)
A novel 3D Tree-based Multilevel FPGA architecture that unifies two unidirectional programmable interconnection network is presented in this paper. In a Tree based architecture, the interconnects are arranged in a multilevel network with the logic blocks placed at different Tree levels using ButterflyFat-Tree network topology. 2D physical layout development(More)
This paper presents an improved Tree-based architecture that unifies two unidirectional programmable networks: A predictible downward network based on the Butter y-Fat-Tree topology, and an upward network using hierarchy. Studies based on Rent's Rule show that switch requirements in this architecture grow slower than in traditional Mesh topologies. New(More)
In this paper, we propose placement and routing techniques to deal with the timing unbalance problem in Wave Dynamic Differential Logic (WDDL) circuits. First, we study the impact of placement on the delay unbalance in a Tree-based FPGA. Then, we propose an adaptation to the Pathfinder routing algorithm to improve the delay balance. The experimental results(More)
We describe a methodology to design and optimize Three-dimensional (3D) Tree-based FPGA by introducing a break-point at particular tree level interconnect to optimize the speed, area, and power consumption. The ability of the design flow to decide a horizontal or vertical network break-point based on design specifications is a defining feature of our design(More)
In this paper, we propose the implementation of multiple defect-tolerant techniques on an SRAM-based FPGA. These techniques include redundancy at both the logic block and intra-cluster interconnect. In the logic block, redundancy is implemented at the multiplexer level. Its efficiency is analyzed by injecting a single defect at the output of a multiplexer,(More)
In this paper, we propose a 2D and 3D interconnect network based on a Mesh-of-Clusters (MoC) topology for the implementation of an efficient Field Programmable Gate Arrays (FPGA) architecture. Proposed MoC-based FPGA architecture presents a new hierarchical Switch Box (SBs) and depopulated intra-cluster interconnect based on the Butterfly-Fat-Tree (BFT)(More)