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—A unified framework is presented in order to build lattice constellations matched to both the Rayleigh fading channel and the Gaussian channel. The method encompasses the situations where the interleaving is done on the real components or on two-dimensional signals. In the latter case, a simple construction of lattices congruent to the densest binary… (More)

- Adel Ghazel, Emmanuel Boutillon, Jean-Luc Danged, Glenn Gulak, Hcdi Laamari
- 2004

A hardware White Gaussian Noise Generator (WGNG) is developed for mobile communication channel emulation in FPGA circuit. High accuracy, fast and low-cost hardware are reached by combining the Box-Muller and Central limit methods. The performance of the designed model is investigated using MATLAB. The Complexity and the performance level are given for some… (More)

In this paper we present our contribution in terms of synchronization processor for a SoC design methodology based on the theory of the latency insensitive systems (LIS) of Carloni et al. Our contribution consists in IP encapsulation into a new wrapper model which speed and area are optimized and synthetizability guarantied. The main benefit of our approach… (More)

The main problem with the hardware implementation of turbo codes is the lack of paral-lelism in the MAP-based decoding algorithm. This paper proposes to overcome this problem by using a new family of turbo codes called Multiple Slice Turbo Codes. This family is based on two ideas: the encoding of each dimension with P independent tail-biting codes and a… (More)

This paper presents several techniques for the VLSI implementation of the MAP algorithm. In general, knowledge about the implementation of the Viterbi algorithm can be applied to the MAP algorithm. Bounds are derived for the dynamic range of the state metrics which enable the designer to optimize the word length. The computational kernel of the algorithm is… (More)

—Layered decoding is known to provide efficient and high-throughput implementation of LDPC decoders. However, the implementation of the layered architecture is not always straightforward because of the memory access conflicts in the a-posteriori information memory. In this paper, we focus our attention on a particular type of conflict introduced by the… (More)

| Through a rapid survey of the architecture of Low-Density Parity-Check (LDPC) decoders, this paper proposes a general framework to describe and compare LDPC decoder architectures. A set of parameters makes it possible to classify the scheduling of iterative decoders, memory organization and type of check node processors and variable node processors. Using… (More)

An original technique to transform functional representation of the design into a structural representation in form of a data flow graph (DFG) is described. A canonical, word-level data structure, Taylor Expansion Diagram (TED), is used as a vehicle to effect this transformation. The problem is formulated as that of applying a sequence of decomposition cuts… (More)

This paper presents an algorithm for variable ordering for Taylor Expansion Diagrams (TEDs). First we prove that the function implemented by the TED is independent of the order of its variables, and then that swapping of two adjacent variables in a TED is a local permutation similar to that in BDD. These two properties allow us to construct an algorithm to… (More)

—An efficient graph-based method to optimize polynomial expressions in data-flow computations is presented. The method is based on the factorization, common-subexpression elimination , and decomposition of algebraic expressions performed on a canonical Taylor expansion diagram representation. It targets the minimization of the latency and hardware cost of… (More)