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Static power consumption due to excessive leakage currents is a major problem in CMOS digital ICs with gate lengths of 90 nm and below. In this paper the physics and modelling of these currents is discussed, with special emphasis on variability and its effect on the statistical spread of the static power consumption and total power consumption.
There was planed a cycle of works devoted to the title problem. The aim of the first of them was evaluation in our material influence of HPV infection on dysplasia progression of cervical squamous epithelium in correlation to the detected HPV type.
In this paper we analyze the commonly used model of spiral inductor in CMOS circuit. The model and methods for its parameter calculation are presented. The experimental circuit for inductance measurement, designed by authors and produced in CMOS 0.35mum technology, is described. It includes several inductors of different shapes made of metal3 and metal4.… (More)
AnaDig, an IC designed for educational purposes, is described. The teaching goal of the chip is to familiarize the students with the properties of IC devices and basic building blocks. Numerous laboratory experiments are available within the same measurement environment. The temperature dependent characteristics can be obtained. The chip was prototyped and… (More)
A special CAD toolset for process, device and circuit statistical simulation is described. Variability is introduced in the process parameter space, not in the space of parameters of the circuit components. As a result, complex dependencies and correlations between process parameters and circuit performance are taken into account in a realistic way.… (More)
The aim of the study was the estimation of significance of smears containing Atypical Squamous Cells of Undetermined Significance (ASCUS) and presentation the own management of that cases. The study group consisted of 73 non-pregnant women (aged from 21 to 54 years) with ASCUS. The control group included 113 non-pregnant patients (aged between 20 and 57… (More)
This paper describes shortly the methodology of postlayout VLSI chip verification oriented on interconnection parasitic effects. The method for selecting long and neighbouring interconnections is presented. Criteria for choosing the simulation models are described.