Elmet Orasson

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The Internet and multimedia open new possibilities for learning methods. We want to present a learning method uses two levels of teaching: so-called living pictures and laboratory research. On one hand teachers can show in basic training more complex examples and immediate demonstrate the influence of changing parameters by using computer simulated living(More)
This paper presents a hybrid BIST solution for testing systems-on-chip which combines pseudorandom test patterns with stored precomputed deterministic test patterns. A procedure is proposed for fast calculation of the cost of hybrid BIST at different lengths of pseudorandom test to find an optimal balance between test sets, and to perform core test with(More)
– This paper describes a diagnostic software package called Turbo Tester. It contains a variety of tools related to the area of testing and diagnosis of integrated circuits. The range of tools includes test generators, logic and fault simulators, a test optimizer, a module for hazard analysis, built-in self-test simulators, design verification and design(More)
Classical built-in self-test (BIST) approaches are largely based on pseudorandom testing, and using linear feedback shift registers (LFSR) for test set generation and test response compaction. In this paper we are concentrating on one possible extension of the classical BIST, namely hybrid BIST, where pseudorandom test patterns are complemented with(More)
– This paper describes tools used in an e-learning environment developed at Tallinn Technical University in the frames of the project REASON. The environment makes use of a diagnostic software package called Turbo Tester and a set of Java applets. It is aimed at teaching basics as well as advanced topics from the area of digital testing and diagnostics of(More)
An environment targeted to e-learning is presented for teaching advanced test issues in digital electronics. Digital circuits and systems are getting more and more complex, and in the same time the requirements for the quality of systems are getting higher and higher. This is the reason why the importance of testing as an engineering task has started to(More)
The paper presents a new structural fault collapsing method with linear algorithmic complexity to reduce the search space for test generation and fault diagnosis in digital circuits. The method is based on the two phase topology analysis of the circuit description. The first phase of fault collapsing is carried out on the gate level during superposition of(More)