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This paper introduces two novel architectures for parallel decimal multipliers. Our multipliers are based on a new algorithm for decimal carry-save multioperand addition that uses a novel BCD-4221 recoding for decimal digits. It significantly improves the area and latency of the partial product reduction tree with respect to previous proposals. We also(More)
—Two's complement multipliers are important for a wide range of applications. In this paper, we present a technique to reduce by one row the maximum height of the partial product array generated by a radix-4 Modified Booth Encoded multiplier, without any increase in the delay of the partial product generation stage. This reduction may allow for a faster(More)
—We present the algorithm and architecture of a BCD parallel multiplier that exploits some properties of two different redundant BCD codes to speedup its computation: the redundant BCD excess-3 code (XS-3), and the overloaded BCD representation (ODDS). In addition, new techniques are developed to reduce significantly the latency and area of previous(More)
CORDIC (Coordinate Rotation Digital Computer) is a well known hardware algorithm for computing various elementary functions. In this work two 32 bit radix 4 CORDIC architectures, unfolded and folded are implemented on available FPGA. The unfolded pipelined architecture consists of a linear array of modules in each of which a micro rotation is carried out.(More)
In this paper we present the algorithm and architecture a radix-10 floating-point divider based on an SRT non-restoring digit-by-digit algorithm. The algorithm uses conventional techniques developed to speed-up radix-2<sup>k</sup> division such as signed-digit (SD) redundant quotient and digit selection by constant comparison using a carry-save estimate of(More)