Elisardo Antelo

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This paper introduces two novel architectures for parallel decimal multipliers. Our multipliers are based on a new algorithm for decimal carry-save multioperand addition that uses a novel BCD-4221 recoding for decimal digits. It significantly improves the area and latency of the partial product reduction tree with respect to previous proposals. We also(More)
CORDIC (Coordinate Rotation Digital Computer) is a well known hardware algorithm for computing various elementary functions. In this work two 32 bit radix 4 CORDIC architectures, unfolded and folded are implemented on available FPGA. The unfolded pipelined architecture consists of a linear array of modules in each of which a micro rotation is carried out.(More)
Two’s complement multipliers are important for a wide range of applications. In this paper, we present a technique to reduce by one row the maximum height of the partial product array generated by a radix-4 Modified Booth Encoded multiplier, without any increase in the delay of the partial product generation stage. This reduction may allow for a faster(More)
ÐA very-high radix algorithm and implementation for circular CORDIC is presented. We first present in depth the algorithm for the vectoring mode in which the selection of the digits is performed by rounding of the control variable. To assure convergence with this kind of selection, the operands are prescaled. However, in the CORDIC algorithm, the coordinate(More)
In this paper we present the algorithm and architecture a radix-10 floating-point divider based on an SRT non-restoring digit-by-digit algorithm. The algorithm uses conventional techniques developed to speed-up radix-2<sup>k</sup> division such as signed-digit (SD) redundant quotient and digit selection by constant comparison using a carry-save estimate of(More)