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—In this paper, we present an alternative approach to neuromorphic systems based on multi-level resistive memory (RRAM) synapses and deterministic learning rules. We demonstrate an original methodology to use conductive-bridge RAM (CBRAM) devices as, easy to program and low-power, binary synapses with stochastic learning rules. New circuit architecture,(More)
Introduction Aggressive device-scaling and low-power operation trends have improved the silicon economy, but at the cost of intrinsic variability. Thus, future computing systems have to be designed to be immune to, or even exploit, the technology variability and intrinsic stochasticity. Although neuromorphic hardware is ascribed to be tolerant to(More)
— We present an original methodology to design hybrid neuron circuits (CMOS + non volatile resistive memory) with stochastic firing behaviour. In order to implement stochastic firing, we exploit unavoidable intrinsic variability occurring in emerging non-volatile resistive memory technologies. In particular, we use the variability on the 'time-to-set'(More)
Recent announcement of 16Gbits Resistive memory from Sony shows the trend to quickly adopt resistive memories as an alternative to DRAM. However, using ReRAM for embedded computing is still a futuristic goal. This paper approaches two applications based on ReRAM-devices for gaining area, performance or power consumption. The first application is FPGA, one(More)
In this paper, the evolution, limits and challenges of charge-storage Silicon Non Volatile Memory technologies are presented, with a special attention for 3D architectures. Then, new resistive memory technologies are introduced. Main principles, challenges and opportunities are discussed. In particular, an overview of our recent research work on phase(More)
— This paper presents a robust OxRAM-based non-volatile flip-flop (NVFF) solution, designed for deep nano-scaled CMOS technologies. Forming, set and reset operations rely on a reliable design approach using thin gate oxide CMOS. The NVFF is benchmarked against a standard FF in 28nm CMOS FDSOI. Non-volatility is added with minimal impact on the FF(More)