Elio Consoli

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In Part II of this paper, a comparison of the most representative flip-flop (FF) classes and topologies in a 65-nm CMOS technology is carried out. The comparison, which is performed on the energy-delay-area domain, exploits the strategies and methodologies for FFs analysis and design reported in Part I. In particular, the analysis accounts for the impact of(More)
In this paper, an ultra-compact model for nanometer CMOS transistors, suitable for the analysis of digital circuits, is proposed. Starting from modified and more accurate versions of classical compact models, an extremely simple one (nine parameters and piecewise linear versus relationships in both triode and saturation) is extracted. All the main physical(More)
In this paper, the adoption of general metrics of the energy-delay tradeoff is investigated to achieve energyefficient design of digital CMOS very large-scale integrated circuits. Indeed, as shown in a preliminary analysis on the performance of various commercial microprocessors, a wide range of Ei D j metrics is typically adopted. Physical interpretation(More)
In this paper, a general and complete design flow for nanometer flip-flops (FFs) is presented. The proposed design methodology permits to optimize FFs under constraints within the energy-delay space through extensive adoption of the Logical Effort method, which also allows for defining the bounds in the design space search. Transistors sizing is rigorously(More)
Flip-flops (FFs) are key building blocks in the design of high-speed energyefficient microprocessors, as their data-to-output delay (D-Q) and power dissipation strongly affect the processor’s clock period and overall power [1]. From previous analyses [2], the Transmission-Gate Pulsed Latch (TGPL) [3] proved to be the most energy-efficient FF in a large(More)