Elie Maricau

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With further scaling of nanometer CMOS technologies, yield and reliability become an increasing challenge. This paper reviews the most important phenomena affecting yield and reliability. For each effect, the basic physical mechanisms causing the effect and its impact on transistor parameters are described. Possible solutions to cope/handle with these(More)
Integrated analog circuit design in nanometer CMOS technologies brings forth new and significant reliability challenges. Ever-increasing process variability effects and transistor wear-out phenomena such as BTI, hot carrier degradation and dielectric breakdown force designers to use large design margins and to increase the uncertainty on the circuit(More)
This paper discusses an efficient method to analyze the spatial and temporal reliability of analog and digital circuits. First, a SPICE-based reliability simulator with automatic step-size control is proposed. Both hot carrier degradation and negative bias temperature instability are included in the simulator. Next, a method to analyze the interaction(More)
The paper discusses reliability threats and opportunities for analog circuit design in high-k sub-32 nanometer technologies. Compared to older SiO<inf>2</inf> or SiON based technologies, transistor reliability is found to be worse in high-k nodes due to larger oxide electric fields, the severely aggravated PBTI effect and increased time-dependent(More)
Transistor aging effects are more and more a major concern for device scientists, trying to integrate reliable circuits in unreliable ultra-scaled CMOS processes. Circuit design margins, to guarantee reliable analog circuit operation, are no longer sufficient and result in huge circuit overdesign. This paper discusses i) the most important transistor aging(More)
Negative Bias Temperature Instability (NBTI) is one of the most important reliability concerns in nanometer CMOS technologies. Accurate models for aging effects such as NBTI can help a designer in determining and improving circuit lifetime. This paper proposes a comprehensible compact model for reliability simulation of analog integrated circuits. The(More)
Aggressive scaling to nanometer CMOS technologies causes both analog and digital circuit parameters to degrade over time due to die-level stress effects (i.e. NBTI, HCI, TDDB, etc). In addition, failure-time dispersion increases due to increasing process variability. In this paper an innovative methodology to simulate analog circuit reliability is(More)
Reliability is becoming one of the major concerns in designing integrated circuits in nanometer CMOS technologies. Problems related to degradation mechanisms like NBTI or soft breakdown, as well as increased external interference such as caused by crosstalk and EMI, cause time-dependent circuit performance degradation. Variability only makes these things(More)
Stochastic circuit reliability analysis, as decribed in this work, matches the statistical attributes of underlying device fabrics and transistor aging to the spatial and temporal reliability of an entire circuit. For the first time, spatial and temporal stochastic and deterministic reliability effects are handled toghether in an efficient framework. The(More)