Elaheh Bozorgzadeh

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Deep sub micron e ects along with increas ing interconnect densities have increased the complexity of the routing problem Whereas previously we could fo cus on minimizing wirelength we must now consider a vari ety of objectives during routing For example an increased amount of timing restrictions means that we must minimize interconnect delay But(More)
Many reconfigurable architectures offer partial dynamic configurability, but current system-level tools cannot guarantee feasible implementations when exploiting this feature. We present a physically aware hardware-software (HW-SW) scheme for minimizing application execution time under HW resource constraints, where the HW is a reconfigurable architecture(More)
Partial dynamic reconfiguration is a key feature of modern reconfigurable architectures such as the Xilinx Virtex series of devices. However, this capability imposes strict placement constraints such that even exact system-level partitioning (and scheduling) formulations are not guaranteed to be physically realizable due to placement infeasibility. We first(More)
Partial dynamic reconfiguration is a key feature of modern reconfigurable architectures such as the Xilinx Virtex series of devices. However, this capability imposes strict placement constraints such that even exact system-level partitioning (and scheduling) formulations are not guaranteed to be physically realizable due to placement infeasibility. We first(More)
This paper presents a theoretical framework that solves optimally and in polynomial time many open problems in time budgeting. The approach unifies a large class of existing time-management paradigms. Examples include time budgeting for maximizing total weighted delay relaxation, minimizing the maximum relaxation, and min-skew time budget distribution. The(More)
Partial dynamic reconfiguration is an emerging area in FPGA designs which is used for saving device area and cost. In order to reduce the reconfiguration overhead, two consecutive similar sub-designs should be placed in the same locations to get the maximum reuse of common components. This requires that all the future designs be considered while(More)
<i>Predictable routing</i> is the concept of using prespecified patterns to route a net. By doing this, we allow an more accurate prediction mechanism for metrics such as congestion and wirelength earlier in the design flow. Additionally, we can better plan the routes, insert buffers and perform wire sizing earlier. With comparable routing quality, we show(More)
Most of an FPGA s area and delay are due to routing Considering routability at earlier steps of the CAD ow would both yield better quality and faster design process In this paper we discuss the metrics that a ect routability in packing logic into clusters We are presenting a routability driven clustering method for cluster based FPGAs Our method packs LUTs(More)
The global routing problem decomposes the large, complex routing problem into a set of more manageable subproblems. The high correlation between the output of the global router and the detailed router enables the designer to efficiently use the global route to refine the design quickly before running the full detailed route. Hence, routability of the global(More)
Wirelength estimation is one of the most important Rent's rule applications. Traditional Rent exponent extraction is based on recursive bipartitioning. However, the obtained exponent may not be appropriate for wirelength estimation. In this paper, we propose the concepts of partitioning-based Rent exponent and placement-based Rent exponent. The relationship(More)