Eileen You

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Shrinking technology enables designers to integrate more functionality with improved performance and density in ICs; but this improvement comes at cost. The impacts of parasitic are dominating circuit performance with leading edge of technology. This paper first presents the post-layout challenges facing by the designers at advanced technology node and then(More)
This paper presents a practical approach to parasitic extraction enabling accurate timing and crosstalk analyses throughout the design cycle. New error indexes, are first proposed for evaluating the accuracy of flat parasitic extraction. The requirements for extraction in hierarchical design flows are then discussed. The methodology reported aims at(More)
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