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This paper offers an Internet-based environment forenhancing problem-specific design flows with test patterngeneration and fault simulation capabilities. AutomaticTest Pattern Generation (ATPG) and fault simulation toolsat structural and hierarchical levels available at geographicallydifferent places running under the virtual environmentusing the MOSCITO(More)
– This paper describes a diagnostic software package called Turbo Tester. It contains a variety of tools related to the area of testing and diagnosis of integrated circuits. The range of tools includes test generators, logic and fault simulators, a test optimizer, a module for hazard analysis, built-in self-test simulators, design verification and design(More)
A test synthesis and analysis system for teaching graduate and undergraduate courses in integrated circuit design and test has been created at the Technical University of Tallinn in Estonia. The system is called Turbo Tester (TT) and it implements different methods for test pattern generation (random, deterministic, mixed), fault simulation (two-and(More)
Current paper presents a test pattern generation approach based on genetic algorithms. The algorithm is designed so that it allows direct comparison with random methods. Experimental results on ISCAS'85 benchmarks [6] show that the proposed algorithm performs significantly better than similar approach published in [1]. In addition, the test sets generated(More)
A new method for hierarchical fault simulation based on multi-level Decision Diagrams (DD) is proposed. We suppose that a register transfer (RT) level information along with gate-level descriptions for blocks of the RT level structure are available. Decision diagrams (DDs) are exploited as a uniform model for describing circuits at these representation(More)
This paper describes an environment for internet-based collaboration in the field of design and test of digital systems. Automatic Test Pattern Generation (ATPG) and fault simulation tools at behavioral, logical and hierarchical levels available at geographically different places running under the virtual environment using the MOSCITO system are presented.(More)
The paper describes an environment for an Internet-based cooperation in the field of design and test of digital systems. A VLSI design flow is combined with an Internet-based hierarchical automated test pattern generation (ATPG). A novel hierarchical ATPG driven by testability measures is presented. Both, the register-transfer (RT) and the gate level(More)
A novel FPGA design flow combined with automated hierarchical test pattern generation was developed and experimented on a real FPGA circuit for telecommunication. A hierarchical test generator for digital systems described in VHDL is presented. Both, register-transfer (RT) and gate level descriptions are used. Decision diagrams are exploited as a uniform(More)