Learn More
—This paper presents a new signature monitoring technique , CFCSS (Control Flow Checking by Software Signatures); CFCSS is a pure software method that checks the control flow of a program using assigned signatures. An algorithm assigns a unique signature to each node in the program graph and adds instructions for error detection. Signatures are embedded in(More)
This paper proposes a pure software technique, Error Detection by Duplicated Instructions (EDDI), for detecting errors during normal system operation. Compared to other error detection techniques that use hardware redundancy, our method does not require any hardware modifications to add error detection capability to the original system. In EDDI, we(More)
In this correspondence two methods are given for calculating the probability that the output of a general combinational network is 1 given the probabilities for each input being 1. We define the notions of the probability of a signal and signal independence. Then several proofs are given to show the relationship between Boolean operations and algebraic(More)
In many computer systems, the contents of memory are protected by an error detection and correction (EDAC) code. Bit-flips caused by single event upsets (SEUs) are a well-known problem in memory chips and EDAC codes have been an effective solution to this problem. These codes are usually implemented in hardware using extra memory bits and encoding-decoding(More)
The detectability of delay flaws can be improved by testing CMOS IC's with a very low supply voltage-between 2 and 2.5 times the threshold voltage V t of the transistors. A delay flaw is a defect that causes a local timing failure but the failure is not severe enough to cause malfunctioning. Delay flaws caused by degraded signals and gates with lower drive(More)
This paper presents a procedure for synthesizing multilevel circuits with concurrent error detection. All errors caused by single stuck-at faults are detected using a parity-check code. The synthesis procedure (implemented in Stanford CRC's TOPS synthesis system) fully automates the design process and reduces the cost of concurrent error detection compared(More)
During built-in self-test (BIST), the set of patterns generated by a pseudo-random pattern generator may not provide a sufficiently high fault coverage. This paper presents a new technique for synthesizing combinational mapping logic to transform the set of patterns that are generated. The goal is to satisfy test length and fault coverage requirements while(More)