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The use of linear dependency relationships among path delay faults (PDFs) is an effective way to determine circuit timing characteristics. The proposed approach improves the performance of performing a linear dependency check by accelerating the Gauss elimination process. This paper presents new algorithms to represent a PDF with respect to a testable set(More)
A recent decision diagram-based algorithm [12] was able to generate test patterns for each sensitizable path delay fault. Although scalable this approach results to prohibitively long test sets. This paper presents a novel technique to intelligently select paths for compaction. It guarantees optimal compaction subject to the order of processing faults. The(More)
This paper presents a novel approach for identifying non-robustly unsensitizable paths using the bounded gate delay model. It is shown that many non-robust paths will remain undetected unless the delay values are calculated at the path level rather than considering calculations at the circuit level bounded delay. As an initial step a canonical data(More)
This paper presents a novel function-based test generation technique for path delay faults (PDFs) under the launch-off-capture (LOC) scan architecture. The LOC architecture imposes the condition that the second test pattern must be a functional response of the initial scan test pattern. The proposed function-based LOC methodology incorporates traditional(More)
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