Edward D. Moreno

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—This paper presents the concept and preliminary tests in FPGA of a specific architecture for a flexible multicore microcontroller. It is aimed to intermediate complexity embedded applications. A previous exact characterize of the microcontroller model and its target applications is a costly-time task, and it depends mostly on experience of the engineers(More)
The large latency of memory accesses is a major obstacle in obtaining high processor utilization in large scale shared-memory multiprocessors. Access to remote memory is likely to be slow, compared to the ever-increasing speeds of processors. Thus, any scalable architecture must rely on techniques that can cope with the large latency of memory accesses to(More)
To achieve superior performance levels when working with heterogeneous distributed platforms, process-scheduling decisions must be based essentially on the platform's features and on the application's demands. A primary objective of computing systems is the efficient use of available resources. The effective use of these resources in this type of system(More)
This paper presents a specific processor for sensors networks (PERS), in a first approach, we used the point-to-point topology. We highlight its architecture, its limited instruction set, simulations and performance results when executes the AES and DES algorithm. We have implemented several versions of our PERS in FPGAs, our first version (simple(More)
This work shows a new architecture for a VLIW-based cryptoprocessor, which is implemented on FPGAs. The cryptoprocessor was designed to execute symmetric cryptography algorithms preferentially. To do so, special modules (such SBOX and PERBIT for substitution and permutation operations, respectively) were described in order to increase the performance and(More)