Edward D. Moreno

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We investigate the effect that caches, particularly caches for remote accesses, have on the performance of hash join algorithms. The join is a computationally intensive operation of relational databases and is used in many important applications. Thus, there are a considerable number of studies on the parallel hash join. However, most of the previous(More)
—This paper presents the concept and preliminary tests in FPGA of a specific architecture for a flexible multicore microcontroller. It is aimed to intermediate complexity embedded applications. A previous exact characterize of the microcontroller model and its target applications is a costly-time task, and it depends mostly on experience of the engineers(More)
The large latency of memory accesses is a major obstacle in obtaining high processor utilization in large scale shared-memory multiprocessors. Access to remote memory is likely to be slow, compared to the ever-increasing speeds of processors. Thus, any scalable architecture must rely on techniques that can cope with the large latency of memory accesses to(More)
The advent of Dark Silicon as result of the limit on Dennard scaling forced modern processor designs to reduce the chip area that can work on maximum clock frequency. This effect reduced the free gains from Moore's law. This work introduces a less conservative dark silicon estimate based on chip components power density and technological process, so that(More)
This paper proposes a validation method for the design of a CPU on which, in parallel with the development of the CPU, it is also manually described a testbench that performs automated testing on the instructions that are being described. The testbench consists of the original program memory of the CPU and it is also coupled to the internal registers,(More)