Eduardo Gudis

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This paper describes an architecture framework using heterogeneous hardware accelerators for embedded vision applications. This approach leverages the recent single-chip heterogeneous FPGAs that combine powerful multicore processors with extensive programmable gate array fabric on the same die. We present a framework using an extensive library of pipelined(More)
— High-performance dense stereo is a critical component of computer vision applications like 3D reconstruction, robot navigation, and augmented reality. In this paper, we present a low-power, high performance FPGA implementation of a stereo algorithm suitable for embedded real-time platforms. The design is scalable for higher resolution images and frame(More)
Field-Programmable Gate Arrays (FPGAs) have become a mainstay in the digital electronics world both for the ease of implementation as well as their inherent usefulness in incrementally refining hardware designs. When moving to an Application Specific Integrated Circuit (ASIC) or System on a Chip (SoC), verification becomes a very time consuming process,(More)
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