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We present a new architecture for signed multiplication. The proposed architecture maintains the pure form of an array multiplier, exhibiting a much lower overhead than the Booth architecture. We propose a Hybrid encoding for the architectures, which is a compromise between the minimal input dependency presented by the Binary encoding and the low switching(More)
— In the last two decades, many efficient algorithms and architectures have been introduced for the design of low-complexity bit-parallel multiple constant multiplications (MCM) operation which dominates the complexity of many digital signal processing systems. On the other hand, little attention has been given to the digit-serial MCM design that offers(More)
OBJECTIVE To present a novel algorithm for estimating recruitable alveolar collapse and hyperdistension based on electrical impedance tomography (EIT) during a decremental positive end-expiratory pressure (PEEP) titration. DESIGN Technical note with illustrative case reports. SETTING Respiratory intensive care unit. PATIENT Patients with acute(More)
Regional lung perfusion estimated by electrical impedance tomography in a piglet model of lung collapse. assessment of the regional match between alveolar ventilation and perfusion in critically ill patients requires simultaneous measurements of both parameters. Ideally, assessment of lung perfusion should be performed in real-time with an imaging(More)
The multiple constant multiplications (MCM) operation, which realizes the multiplication of a set of constants by a variable, has a significant impact on the complexity and performance of the digital finite impulse response (FIR) filters. Over the years, many high-level algorithms and design methods have been proposed for the efficient implementation of the(More)
This article addresses the problem of finding the fewest numbers of addition and subtraction operations in the multiplication of a constant matrix with an input vector---a fundamental operation in many linear digital signal processing transforms. We first introduce an exact common subexpression elimination (CSE) algorithm that formalizes the minimization of(More)
Existing optimization algorithms for the multiplierless realization of multiple constant multiplications (MCM) typically target the minimization of the number of addition and subtraction operations. Since power dissipation is directly related to the amount of hardware, some power reduction is indirectly achieved by these algorithms. However, in many cases,(More)
Bit-parallel realization of the multiplication of a variable by a set of constants using only addition, subtraction, and shift operations has been explored extensively over the years as large number of constant multiplications dominate the complexity of many digital signal processing systems. On the other hand, digit-serial architectures offer alternative(More)