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We present a new architecture for signed multiplication. The proposed architecture maintains the pure form of an array multiplier, exhibiting a much lower overhead than the Booth architecture. We propose a Hybrid encoding for the architectures, which is a compromise between the minimal input dependency presented by the Binary encoding and the low switching… (More)

Abstract: This paper addresses the use of alternative codes for arithmetic operators. The objective is twofold. First, to investigate operand codes that yield simpler, i.e., power efficient, arithmetic modules. Second, to investigate signal encodings that lead to the reduction of the switching activity in the data buses. Although signal correlation is more… (More)

- T. Weber, I. Maniatis, +4 authors E. Schulz
- 2002

- Levent Aksoy, Cristiano Lazzari, Eduardo Costa, Paulo F. Flores, José C. Monteiro
- IEEE Trans. VLSI Syst.
- 2013

— In the last two decades, many efficient algorithms and architectures have been introduced for the design of low-complexity bit-parallel multiple constant multiplications (MCM) operation which dominates the complexity of many digital signal processing systems. On the other hand, little attention has been given to the digit-serial MCM design that offers… (More)

- Levent Aksoy, Eduardo Costa, Paulo F. Flores, José C. Monteiro
- ACM Great Lakes Symposium on VLSI
- 2011

Existing optimization algorithms for the multiplierless realization of multiple constant multiplications (MCM) typically target the minimization of the number of addition and subtraction operations. Since power dissipation is directly related to the amount of hardware, some power reduction is indirectly achieved by these algorithms. However, in many cases,… (More)

- Levent Aksoy, Eduardo Costa, Paulo F. Flores, José C. Monteiro
- ACM Trans. Design Autom. Electr. Syst.
- 2012

This article addresses the problem of finding the fewest numbers of addition and subtraction operations in the multiplication of a constant matrix with an input vector---a fundamental operation in many linear digital signal processing transforms. We first introduce an exact common subexpression elimination (CSE) algorithm that formalizes the minimization of… (More)

- Levent Aksoy, Eduardo Costa, Paulo F. Flores, José C. Monteiro
- 2012 Design, Automation & Test in Europe…
- 2012

The multiple constant multiplications (MCM) operation, which realizes the multiplication of a set of constants by a variable, has a significant impact on the complexity and performance of the digital finite impulse response (FIR) filters. Over the years, many high-level algorithms and design methods have been proposed for the efficient implementation of the… (More)

I. INTRODUCTION Multiplication of a variable with a set of constants, known also as the MCM operation, is a central operation and performance bottleneck in many DSP applications such as, error correcting codes, linear DSP transforms, and Finite Impulse Response (FIR) filters. In hardware, the multiplication operation is considered to be expensive, as it… (More)

- Levent Aksoy, Cristiano Lazzari, Eduardo Costa, Paulo F. Flores, José C. Monteiro
- ACM Great Lakes Symposium on VLSI
- 2011

Bit-parallel realization of the multiplication of a variable by a set of constants using only addition, subtraction, and shift operations has been explored extensively over the years as large number of constant multiplications dominate the complexity of many digital signal processing systems. On the other hand, digit-serial architectures offer alternative… (More)

- Levent Aksoy, Eduardo Costa, Paulo F. Flores, José C. Monteiro
- Microprocessors and Microsystems - Embedded…
- 2011