Eduard Fernandez-Alonso

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The aim of this paper is to give briefing of the concept of network-on-chip and programming model topics on multiprocessors system-on-chip world, an attractive and relatively new field for academia. Numerous proposals from academia and industry are selected to highlight the evolution of the implementation approaches both on NoC proposals and on programming(More)
There is some consensus that Embedded and HPC domains have to create synergies to face the challenges to create, maintain and optimize software for the future many-core platforms. In this work we show how some HPC performance analysis methods can be successfully adapted to the embedded domain. We propose to use Virtual Prototypes based on Instruction Set(More)
— The number of resources available in largest reconfigurable devices enables the synthesis of systems with more than 100 Soft-Core processors. Although being a feasible and attainable alternative, few such systems have been built and few works propose methods to create, program and optimize this kind of systems. In this work we present a methodology that(More)
Reconfigurable parallel computing is required to provide high-performance embedded computing, hide hardware complexity, boost software development, and manage multiple workloads when multiple applications are running simultaneously on the emerging network-on-chip (NoC)-based multiprocessor systems-on-chip (MPSoCs) platforms. In these type of systems, the(More)
License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. Multi-soft-core systems are a viable and interesting solution for embedded systems that need a particular tradeoff between performance , flexibility and development speed. As the growing capacity allows it, many-soft-cores are(More)
—Modern top of the line FPGAs can already host hundreds of simple soft-core processors. Because soft-cores often support floating point units through external interfaces this opens the door to explore the convenience for sharing the floating point units among a number of processors in many-soft-cores. We build two variants of a many-soft-core with 16 NIOSII(More)
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