Edoardo Fusella

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The choice of the communication topology in many systems is of vital importance because it affects the entire inter-component data traffic and impacts significantly the overall system performance and cost. On the other hand, there is a very large spectrum of interconnection topologies that potentially meet given communication requirements, determining(More)
Next-generation chip multiprocessors will require communication performance levels that cannot be achieved by traditional electronic ON-chip interconnects. Silicon photonics has recently emerged as a promising alternative to handle future communication needs thanks to the ultrahigh bandwidth and low power consumption. Optical networks-on-chip (ONoCs) are(More)
While providing a promising solution for high-performance on-chip communication, photonic networks-on-chip suffer from insertion loss and crosstalk noise, which may severely constrain their scalability. In this paper, we introduce a methodology and a related tool, PhoNoCMap, for the design space exploration of optical NoCs mapping solutions, which(More)
Multiprocessor Systems-on-Chip (MPSoC) applications can rely today on a very large spectrum of interconnection topologies potentially meeting given communication requirements, determining various trade-offs between cost and performance. Building interconnects that enable concurrent communication tasks introduces decisive opportunities for reducing the(More)
This work proposes an automated methodology for optimizing FPGA-based many-core interconnect architectures. Based on the application communication requirements, the methodology concurrently defines the structure of the interconnect and the communication task scheduling, taking into account possible dependencies between tasks under given area constraints.(More)
Future many-core systems will require energy-efficient, high-throughput and low-latency communication architectures. Silicon Photonics appears today as a promising solution to achieve these goals. However, the photonics inability to perform inflight buffering and logic suggests the use of Hybrid Photonic-Electronic architectures. In order to exploit the(More)
Silicon photonics appears today a promising solution to handle future communication needs. However, photonic networks-on-chip suffer from crosstalk noise which affects the signal-to-noise ratio (SNR) constraining the network scalability. In this paper, we first formulate the problem of crosstalk-aware mapping and then we propose an algorithm which(More)