Edmund J. Sprogis

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integration technology S. J. Koester A. M. Young R. R. Yu S. Purushothaman K.-N. Chen D. C. La Tulipe, Jr. N. Rana L. Shi M. R. Wordeman E. J. Sprogis An overview of wafer-level three-dimensional (3D) integration technology is provided. The basic reasoning for pursuing 3D integration is presented, followed by a description of the possible process variations(More)
of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection J. U. Knickerbocker P. S. Andry L. P. Buchwalter A. Deutsch R. R. Horton K. A. Jenkins Y. H. Kwark G. McVicker C. S. Patel R. J. Polastre C. Schuster A. Sharma S. M. Sri-Jayantha C. W. Surovic C. K. Tsang B. C. Webb S. L. Wright S. R.(More)
dimensional silicon integration J. U. Knickerbocker P. S. Andry B. Dang R. R. Horton M. J. Interrante C. S. Patel R. J. Polastre K. Sakuma R. Sirdeshmukh E. J. Sprogis S. M. Sri-Jayantha A. M. Stephens A. W. Topol C. K. Tsang B. C. Webb S. L. Wright Three-dimensional (3D) silicon integration of active devices with through-silicon vias (TSVs), thinned(More)
technology with through-silicon vias and low-volume leadfree interconnections K. Sakuma P. S. Andry C. K. Tsang S. L. Wright B. Dang C. S. Patel B. C. Webb J. Maria E. J. Sprogis S. K. Kang R. J. Polastre R. R. Horton J. U. Knickerbocker Three-dimensional (3D) integration using through-silicon vias (TSVs) and low-volume lead-free solder interconnects allows(More)
System-on-chip (SOC) and system-on-package (SOP) technologies each have advantages depending on application needs. As system architects and designers leverage ever-increasing CMOS technology densities, a range of two and three dimensional silicon integration technologies are emerging which likely support next generation high-volume electronic applications(More)
with C4 technology B. Dang S. L. Wright P. S. Andry E. J. Sprogis C. K. Tsang M. J. Interrante B. C. Webb R. J. Polastre R. R. Horton C. S. Patel A. Sharma J. Zheng K. Sakuma J. U. Knickerbocker Three-dimensional (3D) integration technology promises to continue enhancing integrated-circuit system performance with high bandwidth, low latency, low power, and(More)
GaN-based high electron mobility transistors (HEMTs) were fabricated on 200-mm silicon-oninsulator (SOI) substrates possessing multiple crystal orientations. These SOI substrates have the Si (100)-SiO2Si (111) structure, which allows Si (111) to be exposed below the buried oxide to enable GaN epitaxial growth adjacent to Si (100). The current collapse in(More)
Three novel CSP pad designs in a 0.18mum CMOS image sensor Cu interconnect technology were analyzed for use with a wafer level CSP (WLCSP) package. The CSP pad designs used various combinations of available aluminum and tungsten interconnect levels in order to improve the cross-sectional area without increasing the total stack height of the Cu interconnect(More)
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