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A time-interleaved ADC is presented with 16 channels, each consisting of two Successive Approximation (SA) ADCs in a pipeline configuration. Three techniques are presented to increase the speed of an SA-ADC. Single channel performance is 6.9 ENOB at an input frequency of 4 GHz. Multi-channel performance is 7.7 ENOB at 1.35 GS/s with an ERBW of 1 GHz and a(More)
Future systems powered by energy scavenging, e.g., wireless sensor nodes, demand μW-range ADCs with no static bias currents in order to have a power dissipation proportional to the sample rate. An ADC that meets these requirements by using a charge-redistribution DAC, a dynamic 2-stage comparator, and a delay-line-based controller is realized in CMOS.(More)
The bandwidth of global on-chip interconnects in modern CMOS processes is limited by their high resistance and capacitance [1]. Repeaters that are used to speed up these interconnects consume a considerable amount of power [2] and area. Recently published techniques [1-4] increase the achievable data rate at the cost of high static power consumption,(More)
—Crosstalk limits the achievable data rate of global on-chip interconnects on large CMOS ICs. This is especially the case, if low-swing signaling is used to reduce power consumption. Differential interconnects provide a solution for most crosstalk and noise sources, but not for neighbor-to-neighbor crosstalk in a data bus. This neighbor-to-neighbor(More)
—This paper presents a set of circuit techniques to achieve high data rate point-to-point communication over long on-chip RC-limited wire-pairs. The ideal line termination impedances for a flat transfer function with linear phase (pure delay) are derived, using an s-parameter wire-pair model. It is shown that a driver with series capacitance on the one hand(More)
The on-chip communication is getting more attention, as (global) interconnects are rapidly becoming a speed, power and reliability bottleneck for digital systems [1]. Technological advances such as copper interconnects and low-k dielectrics are not sufficient to let the interconnect bandwidth keep up with the advances in transistor speeds. From a(More)
Both ring oscillators and relaxation oscillators are subsets of RC oscillators featuring large tuning ranges and small areas. Figure 19.5.1 shows a typical relaxation oscillator with a capacitor and two switched current sources. Such relaxation oscillators have two advantages with respect to ring oscillators: 1) they have a constant frequency tuning gain;(More)