Ed van Tuijl

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Figure 12.4.1 shows a DAC based on charge redistribution, with a binary-weighted capacitor array [1]. The left side of every capacitor can be switched between a low reference voltage, Vref-, and a high reference voltage, Vref+, using a simple digital inverter. If the left side of capacitor CMSB is switched from low to high, the step on output VDAC is ΔVDAC(More)
The bandwidth of global on-chip interconnects in modern CMOS processes is limited by their high resistance and capacitance [1]. Repeaters that are used to speed up these interconnects consume a considerable amount of power [2] and area. Recently published techniques [1-4] increase the achievable data rate at the cost of high static power consumption,(More)
Networks on chips (NoCs) are becoming popular as they provide a solution for the interconnection problems on large integrated circuits (ICs). But even in a NoC, link-power can become unacceptably high and data rates are limited when conventional data transceivers are used. In this paper, we present a low-power, high-speed source-synchronous link transceiver(More)
This paper presents a set of circuit techniques to achieve high data rate point-to-point communication over long on-chip RC-limited wire-pairs. The ideal line termination impedances for a flat transfer function with linear phase (pure delay) are derived, using an s-parameter wire-pair model. It is shown that a driver with series capacitance on the one hand(More)
Crosstalk limits the achievable data rate of global on-chip interconnects on large CMOS ICs. This is especially the case, if low-swing signaling is used to reduce power consumption. Differential interconnects provide a solution for most crosstalk and noise sources, but not for neighbor-to-neighbor crosstalk in a data bus. This neighbor-to-neighbor crosstalk(More)
From a circuit-design perspective, a general solution is the use of repeaters, but at the expense of area and power. Another proposed solution [2] uses low-swing signaling over differential 10mm aluminum interconnects, but with the requirement of clocked switches along the wire, increasing the already troublesome clock-load. In [3], it is proposed to use(More)
This paper proposes the use of a variable-gain amplifier instead of a hard limiter for amplitude modulation (AM) suppression with low AM-PM (phase modulation) conversion. A hard limiter shows phase shift variations through inputamplitude dependent changes in output waveform, combined with bandwidth limitations. It is shown that these can be kept small only(More)
Both ring oscillators and relaxation oscillators are subsets of RC oscillators featuring large tuning ranges and small areas. Figure 19.5.1 shows a typical relaxation oscillator with a capacitor and two switched current sources. Such relaxation oscillators have two advantages with respect to ring oscillators: 1) they have a constant frequency tuning gain;(More)