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A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time
TLDR
A latch-type voltage sense amplifier in 90nm CMOS is designed with a separated input and cross-coupled stage for fast operation over a wide common-mode voltage range. Expand
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A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC
TLDR
An ADC for energy scavenging is proposed using a charge-redistribution DAC, a dynamic 2-stage comparator, and a delay-line-based controller realized in CMOS. Expand
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A 10-bit Charge-Redistribution ADC Consuming 1.9 $\mu$W at 1 MS/s
TLDR
This paper presents a 10 bit successive approximation ADC that has been implemented in 65 nm CMOS for which technology scaling is advantageous. Expand
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Power Efficient Gigabit Communication Over Capacitively Driven RC-Limited On-Chip Interconnects
TLDR
This paper presents a set of circuit techniques to achieve high data rate point-to-point communication over long on-chip RC-limited wire-pairs. Expand
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Low-Power, High-Speed Transceivers for Network-on-Chip Communication
TLDR
We present a low-power, high-speed source-synchronous link transceiver which enables a factor 3.3 reduction in link power together with an 80% increase in data-rate. Expand
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Intrinsic 1/f device noise reduction and its effect on phase noise in CMOS ring oscillators
This paper gives experimental proof of an intriguing physical effect: periodic on-off switching of MOS transistors in a CMOS ring oscillator reduces their intrinsic 1/f noise and hence theExpand
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Audio at low and high power
TLDR
An overview is presented of recent developments in the analog boundaries of the audio chain. Expand
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A 0.28pJ/b 2Gb/s/ch Transceiver in 90nm CMOS for 10mm On-Chip interconnects
TLDR
A low-swing transceiver for 10mm-long 0.54mum-wide on-chip interconnects is presented. Expand
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A 90μW 12MHz Relaxation Oscillator with a -162dB FOM
Both ring oscillators and relaxation oscillators are subsets of RC oscillators featuring large tuning ranges and small areas. Such relaxation oscillators have two advantages with respect to ringExpand
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A Time-Interleaved Track & hold in 0.13 μm CMOS sub-sampling a 4 GHz signal with 43 dB SNDR
A 16-channel time-interleaved track and hold is presented. Three techniques are introduced enabling a high bandwidth and linearity and good timing alignment. Integrated ADCs are used to evaluate theExpand
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