E. V. Tuijl

Publications
Influence

A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time

D. Schinkel, E. Mensink, E. Klumperink, E. V. Tuijl, B. Nauta
Computer Science, Mathematics
IEEE International Solid-State Circuits…
18 June 2007

A latch-type voltage sense amplifier in 90nm CMOS is designed with a separated input and cross-coupled stage for fast operation over a wide common-mode voltage range. Expand

A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC

M. V. Elzakker, E. V. Tuijl, P. Geraedts, D. Schinkel, E. Klumperink, B. Nauta
Engineering, Computer Science
IEEE International Solid-State Circuits…
5 February 2008

An ADC for energy scavenging is proposed using a charge-redistribution DAC, a dynamic 2-stage comparator, and a delay-line-based controller realized in CMOS. Expand

A 10-bit Charge-Redistribution ADC Consuming 1.9 $\mu$W at 1 MS/s

M. V. Elzakker, E. V. Tuijl, P. Geraedts, D. Schinkel, E. Klumperink, B. Nauta
Engineering, Computer Science
IEEE Journal of Solid-State Circuits
1 May 2010

This paper presents a 10 bit successive approximation ADC that has been implemented in 65 nm CMOS for which technology scaling is advantageous. Expand

Power Efficient Gigabit Communication Over Capacitively Driven RC-Limited On-Chip Interconnects

E. Mensink, D. Schinkel, E. Klumperink, E. V. Tuijl, B. Nauta
Engineering, Computer Science
IEEE Journal of Solid-State Circuits
1 February 2010

This paper presents a set of circuit techniques to achieve high data rate point-to-point communication over long on-chip RC-limited wire-pairs. Expand

Low-Power, High-Speed Transceivers for Network-on-Chip Communication

D. Schinkel, E. Mensink, E. Klumperink, E. V. Tuijl, B. Nauta
Engineering, Computer Science
IEEE Transactions on Very Large Scale Integration…
2009

We present a low-power, high-speed source-synchronous link transceiver which enables a factor 3.3 reduction in link power together with an 80% increase in data-rate. Expand

Intrinsic 1/f device noise reduction and its effect on phase noise in CMOS ring oscillators

Sander Gierkink, E. Klumperink, A. V. D. Wel, G. Hoogzaad, E. V. Tuijl, B. Nauta
Physics
1 July 1999

This paper gives experimental proof of an intriguing physical effect: periodic on-off switching of MOS transistors in a CMOS ring oscillator reduces their intrinsic 1/f noise and hence the… Expand

Audio at low and high power

M. Berkhout, L. Breems, E. V. Tuijl
Engineering, Computer Science
ESSCIRC - 34th European Solid-State Circuits…
18 November 2008

An overview is presented of recent developments in the analog boundaries of the audio chain. Expand

A 0.28pJ/b 2Gb/s/ch Transceiver in 90nm CMOS for 10mm On-Chip interconnects

E. Mensink, D. Schinkel, E. Klumperink, E. V. Tuijl, B. Nauta
Engineering, Computer Science
IEEE International Solid-State Circuits…
18 June 2007

A low-swing transceiver for 10mm-long 0.54mum-wide on-chip interconnects is presented. Expand

A 90μW 12MHz Relaxation Oscillator with a -162dB FOM

P. Geraedts, E. V. Tuijl, E. Klumperink, G. Wienk, B. Nauta
Physics, Computer Science
IEEE International Solid-State Circuits…
6 February 2008

Both ring oscillators and relaxation oscillators are subsets of RC oscillators featuring large tuning ranges and small areas. Such relaxation oscillators have two advantages with respect to ring… Expand

A Time-Interleaved Track & hold in 0.13 μm CMOS sub-sampling a 4 GHz signal with 43 dB SNDR

S. Louwsma, E. V. Tuijl, M. Vertregt, B. Nauta
Engineering, Computer Science
IEEE Custom Integrated Circuits Conference
16 September 2007

A 16-channel time-interleaved track and hold is presented. Three techniques are introduced enabling a high bandwidth and linearity and good timing alignment. Integrated ADCs are used to evaluate the… Expand

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