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A 0.063 µm2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch
We demonstrate the smallest FinFET SRAM cell size of 0.063 µm2 reported to date using optical lithography. The cell is fabricated with contacted gate pitch (CPP) scaled to 80 nm and fin pitch scaledExpand
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Ultra-thin-body and BOX (UTBB) fully depleted (FD) device integration for 22nm node and beyond
We present UTBB devices with a gate length (L<inf>G</inf>) of 25nm and competitive drive currents. The process flow features conventional gate-first high-k/metal and raised source/drains (RSD). BackExpand
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Impact of back bias on ultra-thin body and BOX (UTBB) devices
We present a detailed study of back bias (V<inf>bb</inf>) impact on UTBB devices with a gate length (L<inf>G</inf>) of 25nm and BOX thicknesses (TBOX) of 25nm and 10nm, respectively. It is reportedExpand
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Mainstreaming of the SOI technology
Partially-depleted deep sub-micron CMOS on SOI technology is becoming a mainstream technology. This technology offers 20-35% performance gain over a bulk technology implemented with the sameExpand
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A Silicon Single-Electron Transistor Memory Operating at Room Temperature
A single-electron memory, in which a bit of information is stored by one electron, is demonstrated at room temperature. The memory is a floating gate metal-oxide-semiconductor transistor in siliconExpand
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RTA-Driven Intra-Die Variations in Stage Delay, and Parametric Sensitivities for 65nm Technology
We report, for the first time, a detailed study of intra-die variation (IDV) of CMOS inverter delay for the 65nm technology, driven by mm-scale variations of rapid thermal annealing (RTA). We findExpand
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High performance 32nm SOI CMOS with high-k/metal gate and 0.149µm2 SRAM and ultra low-k back end with eleven levels of copper
This work presents a 32 nm SOI CMOS technology featuring high-k/metal gate and an SRAM cell size of 0.149 mum2. Vmin operation down to 0.6 V in a 16 Mb SRAM array test vehicle has been demonstrated.Expand
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Partially-depleted SOI technology for digital logic
This partially-depleted (PD) silicon on insulator (SOI) technology results in 20-35% performance gain over a comparable bulk technology. A number of SOI-unique effects that complicate device andExpand
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First demonstration of high-Ge-content strained-Si1−xGex (x=0.5) on insulator PMOS FinFETs with high hole mobility and aggressively scaled fin dimensions and gate lengths for high-performance
For the first time, we report fabrication and characterization of high-performance s-Si<sub>1-x</sub>Ge<sub>x</sub>-OI (x~0.5) pMOS FinFETs with aggressively scaled dimensions. We demonstrateExpand
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High-performance nMOSFET with in-situ phosphorus-doped embedded Si:C (ISPD eSi:C) source-drain stressor
For the first time, embedded Si:C (eSi:C) was demonstrated to be a superior nMOSFET stressor compared to SMT or tensile liner (TL) stressors. eSi:C nMOSFET showed higher channel mobility and driveExpand
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