E. Kofi Vida-Torku

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A relationship between the quality level of a multichip module package and test coverage is established. A fault model for each stage of assembly of the package is assumed and the contribution of each of these stages to the quality level is assessed to produce the required relationship to test coverage achieved through test generation programs.
The PowerPC 603 1 microprocessor is a powerful lowcost implementation of the PowerPC ArchitectureTM specification. The structured design, logic verification and test data generation methodologies of the 603 are presented in this paper. The success of these methodologies has been demonstrated by meeting the 603’s aggressive time-to-market goals. 1.0 The(More)
The use of Petri nets to model the register transfers and change of control states in a sequential machine described in a Computer Hardware Design Language (CHDL) with the aim of guiding state space searches is proposed. Each fault to be detected defines a set of goal nodes for the state space search. These goal nodes together with a CHDL description of the(More)
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