E. Carlisle

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This paper presents a novel FPGA-based architecture for the Speeded-Up Robust Feature (SURF) extractor. By leveraging the inherent parallelism of the SURF algorithm, we designed a fully pipelined architecture implemented on the FPGA fabric of a Xilinx Zynq-7020 device (XC7Z020CLG484-1). Compared with other high-performing SURF designs in the literature, our(More)
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