E. Cantó

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In this paper we shall address the paradigms of evolutionary and self-repairing hardware using a new family of programmable devices, called FIPSOC (Field Programmable System On a Chip). The most salient feature of these devices is the integration on a single chip of a programmable digital section, a programmable analog section and a general-purpose(More)
Most partitioning algorithms have been developed for conventional programmable logic (especially FPGAs), being their main goal the minimisation of the signals constituting the interface (cutsize) between partitions, while balancing partition sizes. New families of dynamic reconfigurable programmable logic (DRPL) offer new possibilities to improve functional(More)
Example 1, StReAm, applies the object-oriented design methodology to high-level programming of data streaming applications. While conventional CAD/compiler systems for FPGAs make it very difficult to explore arithmetic optimizations, StReAm offers the flexibility to adapt the number representation, precision, and arithmetic algorithm to the particular needs(More)
In this paper we address the problems posed when Artificial Neural Networks models are implemented in programmable digital hardware. Within this context, we shall especially emphasise the realisation of the arithmetic operators required by these models, since it constitutes the main constraint (due to the required amount of resources) found when they are to(More)
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