Dwayne Burns

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An experimental simulation technique is introduced to study memory constraints affecting comprehension of embedded sentences. Memory for embedded structure is measured in a pairing task that simulates requirements imposed by sentence comprehension. With increasing memory load (number of embeddings), the rate of performance decline is consistent across all(More)
High performance Internet traffic inspection and layer-7 content analysis have become essential functions of high speed networks. Over the past decade several DPI systems have evolved targeting specific issues related to traffic management, user/application policing, intrusion detection/prevention, URL/malicious/unwanted content filtering. Snort, OpenDPI,(More)
This paper discusses the need for new high-speed hardware architectures for future networks and in particular the need for high speed, high capacity shared buffer designs. An implementation of such a buffer using FPGA technology utilizing RLDRAM II is presented. The architecture that has been derived and implemented operated at 12.8 Gbps and is scalable up(More)
We analyze the effect of different pulse shaping filters on the orthogonal frequency division multiplexing (OFDM) based wireless local area network (LAN) systems in this paper. In particular, the performances of the square root raised cosine (RRC) pulses with different rolloff factors are evaluated and compared. This work provides some guidances on how to(More)
Pattern matching in network applications is characterized by intensive computation. In conventional hardware accelerating methods, performance versus cost is a trade-off. In this paper, we proposed a new Hash-CAM hybrid architecture using state-of-the-art FPGA technology that is customized for a given pattern matching problem for DPI.
This paper presents the design and implementation of a fast shared packet buffer for throughput rates of at least 10 Gbps using RLDRAM II memory. A complex packet buffer controller is implemented on an Altera FPGA and interfaced to the memory. Four RLDRAM II devices are combined to store the packet data and one RLDRAM II device is used to store a(More)
Double Data Rate (DDR) SDRAMs have been prevalent in the PC memory market in recent years and are widely used for networking systems. These memory devices are rapidly developing, with high density, high memory bandwidth and low device cost. However, because of the high-speed interface technology and complex instruction-based memory access control, a(More)
This paper presents the design and implementation of a high performance baseband transceiver targeted for System on a Chip (SoC). The presented architecture utilizes a 4×4 Multiple-Input Multiple-Output Orthogonal Frequency Division Multiplexing (MIMO-OFDM) system and is capable of enabling greater than 1Gbps wireless transmission. A complex channel(More)
Because the speed degradation and on-chip resources limit large CAM applications on SoCs and FPGAs, Hash-CAM architectures are attractive concepts combining the space efficiency of hashing algorithm and fast lookup character of the CAM for collision resolutions. In proposed Hash-CAM circuit, single and double hashing schemes are explored and compared. It(More)