Dusan Petranovic

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—In this paper, we propose a compact on-chip interconnect model for full-chip simulation. The model consists of two components, a quasi-three-dimensional (3-D) capacitance model and an effective loop inductance model. In the capacitance model, we propose a novel concept of effective width () for a 3-D wire, which is derived from an analytical(More)
Inserting metal fill to improve inter-level dielectric thickness planarity is an essential part of the modern design process. However, the inserted fill shapes impact the performance of signal interconnect by increasing capacitance. In this paper, we analyze and model the impact of the metal dummy on the signal capacitance with various parameters including(More)
Currently, hardware intellectual property (IP) is delivered at three levels of abstraction: hard, firm, and soft. In order to further enhance performance, efficiency, and flexibility of IP design, we have developed a new approach for designing hardware and software IP called MetaCores. The new design approach starts at the algorithm level and leverages on(More)
In this paper, we present a multiple-TSV based TSV-to-TSV coupling model and extraction methods that consider the impact of depletion region, the silicon substrate effect, and the electrical field distribution around TSVs. Our studies show that these factors have a significant impact on the individual and full-chip scale TSV-to-TSV coupling. Our effort(More)
A complete modal analysis is introduced to derive the crosstalk voltage waveform in multiconductor coupled systems. In addition to the capacitance and inductance matrices, it also includes a resistance matrix. The off-diagonal terms of the resistance matrix are related to the return path, which is important for accurate noise modeling at high frequency. It(More)
We have created a stochastic impulse-response (IR) moment-extractionalgorithm for RC circuit networks. It employs anewly discovered Feynman Sum-over-Paths Postulate. Fullparallelism has been preserved. Numerical verification resultsfor coupled RC lines confirmed rapid convergence. We believethis algorithm may find useful application in massively(More)
In this paper, for the first time, we model and extract the parasitic capacitance between TSVs and their surrounding wires in 3D IC. For a fast and accurate full-chip extraction, we propose a pattern-matching-based algorithm that considers the physical dimensions of TSVs and neighboring wires and captures their field interactions. Our extraction method is(More)
—This correspondence presents an analysis of the finite register length influence on the accuracy of results obtained by the time–frequency distributions (TFD's). In order to measure quality of the obtained results, the variance of the proposed model is found, signal-to-quantization noise ratio (SNR) is defined, and appropriate expressions are derived.(More)
In this paper analytical expressions are derived for effective load capacitances of <i>RLC</i> interconnects to accurately estimate both the propagation delay and transition time at the output of a CMOS gate. The new effective capacitance calculation technique poses no extra complexity as compared to the <i>RC</i> based approaches but can accommodate(More)
This paper presents a silicon effect-aware multiTSV model. Through-silicon-via (TSV) depletion region, silicon substrate discharging path and electrical field distribution around TSV neighbor are modeled and studied in full-chip design. Verification with field solver and full-chip TSV-to-TSV coupling analysis in both the worst case and the average case show(More)