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This paper proposes an efficient and simple architecture for 9/7 discrete wavelet transform based on distributed arithmetic. To derive new proposed architecture, we consider the periodicity and symmetry of DWT to optimize the performance and reduce the computational redundancy. The inner product of coefficient matrix of DWT is distributed over the input by(More)
More and more communication systems call for an efficient FFT component. This paper implements a real-time FFT processor that performs 1 K point FFT, and, with our strategy, we realize a 16 K point FFT processor by only enlarging the memories and counter in the controller. Finally, we implemented an FFT processor with a Xilinx VirtexII FPGA, which can(More)
Due to its excellent device features, manufacture process compatibility and diversity of the circuit structures, The FinFET is considered appropriate candidate for the conventional bulk-MOSFET in sub-22nm technology nodes. However, the power estimation CAD tools for FinFET are missing at the moment, which mainly results from the absence of FinFET power(More)
The new Binary Offset Carrier (BOC) modulated signal obtains good frequency compatibility with traditional Binary Phase Shift Keying (BPSK) signal. However, it raises new challenge for receiver design, i.e. a qualified BOC signal tracking method to alleviate the tracking ambiguity. The two-dimension correlation is utilized in Double Estimator Technique(More)
In this paper, a control and readout circuit for MEMS vibratory gyroscope is described, including closed- loop driving axis and open-loop sensing axis. Capacitive mismatch auto-compensation has been implemented in this system to suppress the influence to the output due to the mismatch of gyroscope capacitors. The ASIC is fabricated in a 0.35um CMOS process.(More)
With the aggressive scaling of device technology, the leakage power has become the main part of power consumption, which seriously reduces the energy recovery efficiency of adiabatic logic. In this paper, a novel low-power adiabatic logic based on FinFET devices has been proposed. Due to the lower leakage current, higher on-state current and design(More)
A reconfigurable CORDIC demodulator platform and design method for digital-IF receiver is presented. A 2-level FSK demodulator for family network is implemented and tested on that platform with Xilinx VirtexII XC2V1000-4FG256 FPGA. The 2-level FSK noncoherent detector is designed based on counting the zero crossing points using new noise elimination(More)