Learn More
A new energy-efficient switching technique for 2bit /cycle successive approximation register (SAR) analog-to-digital converters (ADCs) is presented. The proposed switching technique achieves 97.91% less switching energy and 75% less total capacitance over the conventional architecture. A LSB correction method is also proposed to relax the accuracy(More)
  • Suparshya Babu Sukhavasi, Susrutha Babu Sukhavasi, +21 authors John P Uyemura
  • 2012
In this paper a new approach of reducing power for a given system is developed that is self resetting logic, a parallel compressor is developed for multiplier by reducing its power with facilitation of this low power logic technique. By using this technique the power dissipation is significantly reduced with respect to other logics. By implementing the(More)
  • 1