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layout size of the designed 256-KBit EEPROM IP is 1765.05μm × 691.71μm.
—In this paper, we design a 1-kb OTP (One-time programmable) memory IP in consideration of BCD process based EM (Electro-migration) and resistance variations of eFuse. We propose a method of precharging BL to VSS before activation of RWL (Read word-line) and an optimized design of read NMOS transistor to reduce read current through a non-programmed cell.… (More)