Douglas H. Summerville

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In this paper we present a study of a prefix routing cache for Internet IP routing. An output port assignment requires one cache memory access when the assignment is found in cache. The cache array is divided into sets that are of variable size; all entries within a set have the same prefix size. The cache is based on a ternary content addressable memory(More)
Data storage is one of the most profitable applications in Clouds. Although a transparent service model is convenient, it may be subject to the loss of data integrity. Our study revealed vulnerabilities in some commercial Cloud storage services. We analyzed the repudiation problem in a Cloud environment. In this paper, we propose a new multi-party(More)
—Given the rapid evolution of attack methods and toolkits, software-based solutions to secure the network infrastructure have become overburdened. The performance gap between the execution speed of security software and the amount of data to be processed is ever widening. A common solution to close this performance gap is through hardware implementation of(More)
— A VLSI implementation of a programmable pipe-lined router scheme for parallel machine interconnection networks is presented in this paper. The implementation is based on a dynamic content-addressable memory (DCAM) that supports unique bit masking per entry. The number of required DCAM entries is extremely small; it is of the same order as the node degree(More)
Data-dependent (DD) permutations (DDP) are discussed as a cryptographic primitive for the design of fast hardware , firmware, and software encryption systems. DDP can be performed with so called controlled permutation boxes (CPB) which are fast while implemented in cheap hardware. The latter defines the efficiency of the embedding of CPB in microcontrollers(More)
* – In recent years, researchers have found that some XOR erasure codes lead to higher performance and better throughput in fault-tolerant distributed data storage applications. However, little consideration has been given to the advantages of parallel processing or hardware implementations taking advantage of the emergence of multi-core processors. This(More)