Douglas Brisbin

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Unique analog product application requirements such as high speed, low noise, low power, high precision and high voltage demand complex analog process technologies. This complexity poses several reliability challenges that are specific to each technology. In this paper some of the key reliability mechanisms in most common analog process technologies are(More)
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We present the cross-identification and source photometry techniques used to process Herschel SPIRE imaging taken as part of the Herschel Multi-Tiered Extragalactic Survey (HerMES). Cross-identifications are performed in map-space so as to minimise source blending effects. We make use of a combination of linear inversion and model selection techniques to(More)
Plasma damage resulting from fluorine doped High Density Plasma Deposition (FHDP) was investigated. A dielectric barrier layer placed either directly under the FHDP or directly over the gate was found to protect the gate oxide from plasma damage. The mechanism by which the dielectric layers counteract plasma damage from upper dielectric layers is(More)
For PMOSFET devices NBTI is a serious reliability concern. Because of recovery effects careful stress and measurement methods must be used to determine threshold voltage degradation. These methods assume that mobility and subthreshold slope degradation are minimal. Recent papers have pointed out that this assumption may not be valid. This paper discusses(More)
NBTI is a serious reliability concern in state of the art PMOSFET devices. The implementation of nitrided gate oxide to prevent boron penetration has aggravated the NBTI issue. Because of relaxation effects careful stress and measurement techniques ("On-the-Fly") must be used for reliable estimation of device lifetime. This abstract describes a unique(More)
Power management devices often require operation in the 20 V to 30 V range. A common choice for the power MOS driver is an n-channel lateral DMOS (N-LDMOS) device. An advantage of N-LDMOS device is that it can easily be integrated within existing technologies to handle a wide range of operating voltages without significant process changes. Because of the(More)
It has been reported that MOSFET hot carrier (HC) performance is degraded by back-end-of-line (BEOL) processing steps such as interlayer dielectric film deposition, passivation, and H/sub 2/ annealing. These effects are associated with the incorporation of additional hydrogen at the Si-SiO/sub 2/ interface states to passivate dangling bonds. This paper(More)