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A low voltage to high voltage level shifter in a low voltage, 0.25/spl mu/m PD SOI process
TLDR
This paper describes a low voltage to high voltage logic level shifter that has been designed entirely in a low breakdown voltage process. Expand
  • 6
Design of a pipelined adder using skew tolerant domino logic in a 0.35 /spl mu/m TSMC process
TLDR
This paper discusses overlapping clocks to eliminate possible sources of overhead by using the concept of time borrowing in the multi-bit carry propagate adder. Expand
  • 5
Characterization of Bitumen Properties Using Microscopy and Near Infrared Spectroscopy: Processability of Oxidized or Degraded Ores
Oxidized or degraded oil sands can exhibit poor processability, which is often not correlated with the fines or clay contents in the ore. Chemical markers (such as low pH and high soluble iron andExpand
  • 14
Forgetful logic circuits for pulse-mode neural networks
TLDR
We introduce a new class of pulse-mode circuit, called forgetful logic. Expand
  • 1
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High impedance nano charger for on-chip 50nAH rated microbatteries
Integrated microbatteries are being currently developed to act as a "micropower" source in microsatellites. They help provide localized current capacities or embedded power supplies at the chipExpand
Integration of IC/EC systems in ITER
The RF heating and current drive (H&CD) systems that are to be installed in ITER during the construction phase, are the electron cyclotron (EC) and ion cyclotron (IC) systems. They are complexExpand
  • 7
Trajectory Inference Using a Motion Sensing Network
TLDR
We present a novel "recombine" proposal for Markov Chain construction and use the new proposal to devise a probabilistic trajectory inference algorithm that generates likely trajectories given raw sensor data. Expand