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In this paper, we present an efficient sequential circuit parallel fault simulator, HOPE, which simulates 32 faults at a time. The key idea incorporated in HOPE is to screen out faults with short propagation paths through the single fault propagation. A systematic method of identifying faults with short propagation paths is presented. The proposed method(More)
This paper presents a low-power design of a motion estimation block targeting for a low-bit rate video codec H.263. The block is based on the Four-Step Search algorithm. The proposed design offers up to 38 % power reduction for logic blocks alone over a " baseline " implementation of the Four-Step Search (4SS) algorithm and up to 58 % power reduction over a(More)
The overall throughput of automatic test equipment (ATE) is sensitive to the download time of test data. An effective approach to the reduction of the download time is to compress test data before the download. The authors introduced a test data compression method which outperforms other methods for compressing test data [8]. Our previous method is based on(More)
In this paper we discuss the design of a CMOS based pulse generator for impulse-based UWB systems. The basic structure of our design involves a power amplifier with four control taps, which essentially decides the shape of the generated pulse. The design is versatile and may be used in a variety of UWB modulation schemes and systems. In addition, this(More)
We present a system which automatically inserts BIST hardware to a circuit described in VHDL. An appropriate VHDL modeling style for automatic insertion of BIST hardware is investigated. Use of BILBO is primarily pursued in the system. Algorithmic and rule-based approaches are used in the insertion of BILBO. Test scheduling and control signal distribution(More)
In this paper, we investigate a new generalized selection combining (GSC) technique and an adaptive rake combining scheme to save the power consumption of mobile rake receivers for wideband CDMA systems. The new GSC technique called minimum selection GSC (MS-GSC) selects a minimum number of rake fingers, while maintaining the combined SNR larger than a(More)
* The VLSI chip in this study has been fabricated in the chip fabrication program of VLSI Design and Education Center (VDEC), the University of Tokyo with the collaboration by Rohm Corporation and Toppan Printing Corporation. Abstract Some open defects in VLSI circuits may cause delay faults, and testing of open defects and delay faults remain difficult(More)