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In this paper, we present an efficient sequential circuit parallel fault simulator, HOPE, which simulates 32 faults at a time. The key idea incorporated in HOPE is to screen out faults with short propagation paths through the single fault propagation. A systematic method of identifying faults with short propagation paths is presented. The proposed method(More)
The overall throughput of automatic test equipment (ATE) is sensitive to the download time of test data. An effective approach to the reduction of the download time is to compress test data before the download. The authors introduced a test data compression method which outperforms other methods for compressing test data [8]. Our previous method is based on(More)
High switching frequency, high resolution digital pulse-width modulator (DPWM) is one of major challenges in the implementation of digital-controlled power converters, especially in the voltage regulator (VR) application. This paper proposes three different digital duty cycle modulation schemes to improve the resolution. Almost 10 times improvement on(More)
Impulse-based ultra wideband (I-UWB) is an attractive radio technology for large ad hoc and sensor networks due to its robustness to harmful multipath effects, sub-centimeter ranging ability, simple hardware, and low radiated power. To scale to large sizes, networks often implement distributed medium access control (MAC) protocols. However, most MAC(More)
The overall throughput of automatic test equipment (ATE) is sensitive to the download time of test data. An effective approach to the reduction of the download time is to compress test data before the download. A compression algorithm for test data should meet two requirements: lossless and simple decompression. In this paper, we propose a new test data(More)
In this paper, we investigate a new generalized selection combining (GSC) technique and an adaptive rake combining scheme to save the power consumption of mobile rake receivers for wideband CDMA systems. The new GSC technique called minimum selection GSC (MS-GSC) selects a minimum number of rake fingers, while maintaining the combined SNR larger than a(More)
* The VLSI chip in this study has been fabricated in the chip fabrication program of VLSI Design and Education Center (VDEC), the University of Tokyo with the collaboration by Rohm Corporation and Toppan Printing Corporation. Abstract Some open defects in VLSI circuits may cause delay faults, and testing of open defects and delay faults remain difficult(More)
In [1]-[2], a highly successy%l parallel fault simulator, called PROOFS, for synchronous sequential circuits has been reported. The performance of PROOFS has been substantially improved in HOPE [3]. In HOPE, a systematic way of screening out faults with short propagation zone is proposed. In this paper, we propose several new techniques which further reduce(More)
In this paper we discuss the design of a CMOS based pulse generator for impulse-based UWB systems. The basic structure of our design involves a power amplifier with four control taps, which essentially decides the shape of the generated pulse. The design is versatile and may be used in a variety of UWB modulation schemes and systems. In addition, this(More)