Donald G. Bailey

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The classic connected components labelling algorithm requires two passes through an image. This paper presents an algorithm that allows the connected components to be analysed in a single pass by gathering data on the regions as they are built. This avoids the need for buffering the image, making it ideally suited for processing streamed images on an FPGA(More)
Classical connected components labelling algorithms are unsuitable for real-time processing of streamed images on an FPGA because they require two passes through the image. Recently, a single-pass algorithm was proposed that avoided the need to buffer an intermediate image. In this paper, a new single pass algorithm is described that is a considerable(More)
The results of research on rank filters are presen ted. The relationship of rank filters with other filters is briefly discussed. The main properties of rank filters are listed and an explanation is given for these properties. Several software and hardware implementations of the filter are described. Major applications to image processing are discussed,(More)
Image super-resolution involves interpolating a non-uniformly sampled composite image at uniform locations of a high-resolution image. Interpolation methods used in the literature are generally based on arbitrary functions. Optimal (in least squares sense) interpolation kernels can be derived if the ground-truth high-resolution data is known, this is(More)
Classical connected components labelling algorithms are unsuitable for real-time processing of streamed images on an FPGA because they require two passes through the image. The basic requirements of connected components analysis are investigated, and this led to a novel single-pass approach that avoids the need to buffer an intermediate image. This is(More)
Bilinear interpolation is often used to improve image quality after performing spatial transformation operations such as digital zooming or rotation. In the traditional case where the input coordinates appear in a raster-based fashion, the required pixel values can be obtained from the previous calculation, the frame buffer and a single line cache. This(More)
Real-time video processing is an image-processing application that is ideally suited to implementation on FPGAs. We discuss the strengths and weaknesses of a number of existing languages and hardware compilers that have been developed for specifying image processing algorithms on FPGAs.We propose VERTIPH, a newmultiple-view visual language that avoids the(More)
In this paper, an adaptive architecture for dynamic management and allocation of on-chip FPGA Block Random Access Memory (BRAM) resources is presented. This facilitates the dynamic sharing of valuable and scarce on-chip memory among several processing elements (PEs), according to their dynamic run-time memory requirements. Different real-time applications(More)
Plants of Metrosideros excelsa Sol. ex Gaertn. ‘Scarlet Pimpernel’, which had undergone reversal of ontogenetic ageing (rejuvenation) following micropropagation, were subjected to shoot and root restriction treatments over 35 weeks to accelerate vegetative phase change. Shoot restriction was imposed by removal of axillary branches, while control plants were(More)